chipsalliance
CHIPS Alliance Joined Jan 2019 View on GitHub
- Stars
- 21,915
- across 118 public repos
- Rank
- #1,695
- of 94,827 organizations, top 2%
- Down 63 places this week
Repositories with 50+ stars
| Rank | Repository | Language | Stars |
|---|---|---|---|
| 13,422 | Chisel: A Modern Hardware Design Language | Scala | 4,832 |
| 17,016 | Rocket Chip Generator | Scala | 3,901 |
| 34,508 | Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server | C++ | 1,974 |
| 49,673 | Random instruction generator for RISC-V processor verification | Python | 1,377 |
| 67,724 | VeeR EH1 core | SystemVerilog | 975 |
| 86,897 | Flexible Intermediate Representation for RTL | Scala | 748 |
| 91,275 | A template project for beginning new Chisel work | Shell | 709 |
| 127,609 | Caliptra IP and firmware for integrated Root of Trust block | 490 | |
| 129,970 | SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX | C++ | 480 |
| 136,315 | FOSS Flow For FPGA | Python | 455 |
| 150,777 | Test suite designed to check compliance with the SystemVerilog standard. | SystemVerilog | 406 |
| 171,412 | VeeR EL2 Core | SystemVerilog | 351 |
| 175,353 | FuseSoC-based SoC for VeeR EH1 and EL2 | Verilog | 342 |
| 182,808 | Scala | 326 | |
| 202,192 | Example designs showing different ways to use F4PGA toolchains. | Verilog | 290 |
| 205,892 | VeeR EH2 core | SystemVerilog | 284 |
| 215,083 | Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format... | C++ | 270 |
| 234,189 | RISC-V RV64GC emulator designed for RTL co-simulation | C++ | 244 |
| 239,934 | SystemVerilog synthesis tool | Verilog | 237 |
| 304,018 | Jupyter Notebook | 178 | |
| 311,270 | Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test | Rust | 173 |
| 332,301 | HW Design Collateral for Caliptra RoT IP | SystemVerilog | 160 |
| 335,751 | C++ | 158 | |
| 339,268 | Chisel/Firrtl execution engine | Scala | 156 |
| 348,454 | Advanced Interface Bus (AIB) die-to-die hardware open source | Verilog | 151 |
| 364,287 | SystemVerilog | 143 | |
| 425,081 | Unit tests generator for RVV 1.0 | Go | 118 |
| 455,871 | FPGA tool performance profiling | Python | 108 |
| 476,980 | FPGA Assembly (FASM) Parser and Generator | Python | 102 |
| 550,054 | OmniXtend cache coherence protocol | TeX | 85 |
| 550,054 | Plugins for Yosys developed as part of the F4PGA project. | Verilog | 85 |
| 594,814 | chipyard in mill :P | Scala | 77 |
| 640,706 | Post-Quantum Cryptography IP Core (ML-DSA and ML-KEM) | SystemVerilog | 70 |
| 655,646 | The specification for the FIRRTL language | TeX | 68 |
| 687,796 | Home of the Advanced Interface Bus (AIB) specification. | 64 | |
| 687,796 | Cap'n Proto | 64 | |
| 704,738 | Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests) | Shell | 62 |
| 732,722 | SystemVerilog | 59 | |
| 742,438 | Nix template for the chisel-based industrial designing flows. | Nix | 58 |
| 763,364 | HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls. | SystemVerilog | 56 |
| 834,145 | A Scala library for Context-Dependent Environments | Scala | 50 |
Among 94,827 organizations
16k–25k stars: 924 organizations, including chipsalliance
Stars along the bottom, and organizations in each band on a log scale
Where the stars are
Languages
- Scala 10.1k stars, 46% · 7 repos
- C++ 3.1k stars, 14% · 5 repos
- SystemVerilog 2.5k stars, 11% · 9 repos
- Python 2k stars, 9% · 4 repos
- Verilog 1.1k stars, 5% · 5 repos
- Shell 771 stars, 4% · 2 repos
- Jupyter Notebook 178 stars, 1% · 1 repo
- Rust 173 stars, 1% · 1 repo
and 4 more languages
When they were made
41 repos with 50+ stars, made between 2014 and 2024
Quick stats
- Next rank
- +10 stars to reach #1,694
- Next milestone
- +13,058 stars to reach the top 1%
- Public repos
- 118, 41 with 50+ stars
- Popular repos
- 29 over 100 stars, 4 over 1k stars
- Top repo
- chisel, #13,422 of all repos, 22% of stars
- Smaller repos
- 979 stars from repos under 50