chipsalliance/Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

by CHIPS Alliance C++ Apache-2.0 licence 90 forks Created Oct 2019 View on GitHub

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480
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#130,342
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#6,912
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68 stars a year since Oct 2019

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