chipsalliance/
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
by CHIPS Alliance C++ Other licence 316 forks Created Nov 2019 View on GitHub
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- 1,974
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- #34,499
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- In C++
- #1,765
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- Popular
- One of 66,291 repos with 1k+ stars
- Yearly average
- 282 stars a year since Nov 2019