WangXuan95
Dr.W.X Joined Jul 2016 2,606 followers View on GitHub
- Stars
- 8,365
- across 36 public repos
- Rank
- #4,030
- of 323,845 users, top 2%
- New on the board this week
Repositories with 50+ stars
| Rank | Repository | Language | Stars |
|---|---|---|---|
| 66,378 | An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器,用于驱动BLDC/PMSM电机。 | Verilog | 998 |
| 70,561 | An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1... | Verilog | 934 |
| 75,500 | Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核 | Batchfile | 869 |
| 104,439 | 一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。 | Bluespec | 612 |
| 139,835 | An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。 | SystemVerilog | 442 |
| 166,883 | An FPGA-based FT232H/FT600 chip controller for rapid data transmission via USB. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。 | Verilog | 362 |
| 166,883 | An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。 | Verilog | 362 |
| 170,216 | This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调试器。 | Verilog | 354 |
| 171,502 | An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器,可以从FAT16或FAT32格式的SD卡中读取文件。 | Verilog | 351 |
| 173,653 | An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器,可实现高压缩率的无损/近无损图像压缩。 | Verilog | 346 |
| 236,688 | Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库,提供算术运算、与浮点数的互相转换,包含单周期和流水线两种实现。 | Verilog | 241 |
| 251,502 | An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。 | Verilog | 224 |
| 328,962 | An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压缩器。输入原始数据,输出标准的GZIP格式,即常见的 .gz / .tar.gz 文件的格式。 | Verilog | 162 |
| 344,689 | An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器,可实现视频压缩。 | Verilog | 153 |
| 352,341 | An FPGA-based NFC (RFID) reader with a simple circuit rather than RFID chips. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器,不需要专门的RFID芯片。 | Verilog | 149 |
| 354,274 | A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。 | SystemVerilog | 148 |
| 370,626 | Imitate SDcard using FPGAs. 使用FPGA模拟伪装SD卡。 | Verilog | 140 |
| 403,475 | 使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例 | 126 | |
| 422,180 | An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器 | Verilog | 119 |
| 455,869 | An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图像解码器,可以从PNG文件中解码出原始像素。 | Verilog | 108 |
| 455,869 | An FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器,用来进行无损图像压缩。 | SystemVerilog | 108 |
| 462,555 | An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII,用来连接LAN8720、KSZ8041TLI-S等百兆以太网PHY芯片。 | Verilog | 106 |
| 476,973 | NBLI is a fast, better lossless image compression algorithm. The optimized version (fNBLI) can get 1.5x compression ratio, 8x faster encoding, and 1.2x faster decoding compared to PNG. It can also... | C++ | 102 |
| 484,542 | An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线),可以从FAT16或FAT32格式的SD卡中读取文件。 | Verilog | 100 |
| 492,022 | 一个针对 PNG 图像文件的有损压缩器,使用 Kmeans 把色彩空间量化压缩到256以下,从而利用 PNG 格式的调色板模式 (Palette) 来缩小文件大小。效果好于 https://tinypng.com | Python | 98 |
| 516,723 | 一个FPGA核心板设计,体积小、低成本、易用、扩展性强。 | Verilog | 92 |
| 530,482 | An FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器,用于通用数据压缩。 | Verilog | 89 |
| 555,254 | Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。 | Verilog | 84 |
| 555,254 | TinyZZZ includes GZIP, LZ4, ZSTD, LZMA compression algorithms written in C language, unlike the official code, this code mainly focuses on simplicity and easy to understand. | C | 84 |
| 600,883 | A comparison of many lossless image compression formats. | Python | 76 |
| 640,713 | 70 | ||
| 752,817 | A lightweight image converter which supports PNG, PNM, BMP, QOI, JPEG-LS, and H.265 intra-frame. | C | 57 |
Among 323,845 users
6.3k–10k stars: 2,566 users, including WangXuan95
Stars along the bottom, and users in each band on a log scale
Where the stars are
Languages
- Verilog 5.5k stars, 65% · 20 repos
- Batchfile 869 stars, 10% · 1 repo
- SystemVerilog 698 stars, 8% · 3 repos
- Bluespec 612 stars, 7% · 1 repo
- Python 174 stars, 2% · 2 repos
- C 141 stars, 2% · 2 repos
- C++ 102 stars, 1% · 1 repo
When they were made
32 repos with 50+ stars, made between 2017 and 2024
Quick stats
- Next rank
- +1 star to reach #4,029
- Next milestone
- +1,564 stars to reach the top 1%
- Public repos
- 36, 32 with 50+ stars
- Popular repos
- 24 over 100 stars
- Top repo
- FPGA-FOC, #66,378 of all repos, 12% of stars
- Smaller repos
- 99 stars from repos under 50