WangXuan95/
Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。
by Dr.W.X Verilog GPL-3.0 licence 42 forks Created Jul 2019 View on GitHub
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