WangXuan95/
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
by Dr.W.X SystemVerilog GPL-3.0 licence 81 forks Created Feb 2019 View on GitHub
- Stars
- 442
- 5% of WangXuan95's stars
- Rank
- #140,315
- of 852,180 repos, top 17%
Among 852,180 repos
400–630 stars: 51,567 repos, including USTC-RVSoC
top 50%top 10%top 1%top 0.1% 
Stars along the bottom, and repos in each band on a log scale
Quick stats
- Next rank
- +1 star to reach #140,033
- Next milestone
- +325 stars to reach the top 10%
- Popular
- One of 490,958 repos with 100+ stars
- Yearly average
- 57 stars a year since Feb 2019