WangXuan95/
This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。
by Dr.W.X Verilog GPL-3.0 licence 55 forks Created Aug 2019 View on GitHub
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