openhwfoundation/
4 stage, in-order, secure RISC-V core based on the CV32E40P
by OpenHW Foundation SystemVerilog Other licence 29 forks Created Feb 2021 View on GitHub
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- 163
- 2% of openhwfoundation's stars
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- #328,392
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- Popular
- One of 490,778 repos with 100+ stars
- Yearly average
- 28 stars a year since Feb 2021