openhwfoundation

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Functional verification project for the CORE-V family of RISC-V cores.

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional...

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

CORE-V Family of RISC-V Cores

Instruction Set Generator initially contributed by Futurewei

4 stage, in-order, compute RISC-V core based on the CV32E40P

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

4 stage, in-order, secure RISC-V core based on the CV32E40P

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

CORE-ET Silicon Platform

CVA6 SDK containing RISC-V tools and Buildroot