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An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Berkeley's Spatial Array Generator

chisel tutorial exercises and answers

educational microarchitectures for risc-v isa

Simple RISC-V 3-stage Pipeline in Chisel

Support for Rocket Chip on Zynq FPGAs

SoftFloat release 3

Hammer: Highly Agile Masks Made Effortlessly from RTL

A Library of Chisel3 Tools for Digital Signal Processing

A Chisel RTL generator for network-on-chip interconnects

The batteries-included testing and formal verification library for Chisel-based RTL designs.

RISC-V Torture Test

Microarchitecture implementation of the decoupled vector-fetch accelerator

Chisel RISC-V Vector 1.0 Implementation

Autocomp: Optimize any AI kernel, anywhere.

An open-source UCIe implementation

An open framework for designing and deploying custom AI-driven HW/SW co-design flows fast

UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

Fork of upstream onnxruntime focused on supporting risc-v accelerators

A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)

TestFloat release 3

A Heterogeneous GPU Platform for AI and Neural Graphics

Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator

Memory System Microbenchmarks

Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC

Z-scale Microarchitectural Implementation of RV32 ISA

A prototype GUI for chisel-development

Tool for converting PyTorch models into raw C codes with minimal dependency and some performance optimizations.