pulp-platform

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

An open-source microcontroller system based on RISC-V

Common SystemVerilog components

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

A dependency management tool for hardware projects.

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

A Fast, Low-Overhead On-chip Network

RISC-V Debug Support for our PULP RISC-V Cores

A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

⛔ DEPRECATED ⛔ Lean but mean RISC-V system!

Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.

An energy-efficient RISC-V floating-point compute cluster.

Generic Register Interface (contains various adapters)

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

GEMM and GEMM-Ops accelerator for PULP systems

The multi-core cluster of a PULP system.

Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software...

Technology dependent cells instantiated in the design for generic process (simulation, FPGA)

A tool to deploy Deep Neural Networks on PULP-based SoC's

pulp_soc is the core building component of PULP based SoCs

DNN Compiler for Heterogeneous SoCs

AXI Adapter(s) for RISC-V Atomic Operations

A SystemVerilog source file pickler.

SystemVerilog modules and classes commonly used for verification

A high-efficiency system-on-chip for floating-point compute workloads.

Simple runtime for Pulp platforms

Simple single-port AXI memory interface

⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform