Xilinx

Python Productivity for ZYNQ

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

Vitis In-Depth Tutorials

Brevitas: neural network quantization in PyTorch

The official Linux kernel from Xilinx

Xilinx Embedded Software (embeddedsw) Development

Vitis Libraries

Dataflow compiler for QNN inference on FPGAs

Xilinx DMA IP Drivers

A close-to-metal Python API for programming AMD Ryzen™ AI NPUs (AI Engines), built on an open-source MLIR-based compiler toolchain.

Quantized Neural Networks (QNNs) on PYNQ

Run Time for AIE and FPGA based platforms

The official Xilinx u-boot repository

Vitis_Accel_Examples

Vitis HLS LLVM source code and examples

Build Customized FPGA Implementations for Vivado

Xilinx Tcl Store

SDAccel Examples

AMD OpenNIC Project Overview

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

Getting Started with Xilinx ML Suite

SystemC/TLM-2.0 Co-simulation framework

Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.

Dataflow QNN inference accelerator examples on FPGAs

DPU on PYNQ

Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)

Vitis HLS Library for FINN

Fork of LLVM to support AMD AIEngine processors

Computer Vision Overlays on Pynq

Collection of Yocto Project layers to enable AMD Xilinx products

RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.

QEMU libsystemctlm-soc co-simulation demos.

Graph Transforms to Quantize and Retrain Deep Neural Nets in TensorFlow

VNx: Vitis Network Examples

AMD OpenNIC Shell includes the HDL source files

SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials

PYNQ support and examples for Kria SOMs

AMD University Program HLS tutorial

Vitis Model Composer Examples and Tutorials

Train and deploy LUT-based neural networks on FPGAs

Kria Vitis platforms and overlays

This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.

Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators

SDAccel Development Environment Tutorials

Python productivity for RFSoC platforms

meta-petalinux distro layer supporting Xilinx Tools

The repository contains the design database and documentation for Electric Drives Demonstration Platform

Xilinx Deep Learning IP

Xilinx Unisim Library in Verilog

AMD OpenNIC driver includes the Linux kernel driver

PYNQ Composabe Overlays

PCI Express controller model

ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communication Framework) ChipScope Server (cs_server).

Alveo Versal Example Design

Yocto Project layer enables AMD Xilinx tools related metadata for MicroBlaze, Zynq, ZynqMP and Versal devices.

Device trees used by QEMU to describe the hardware

Open-sourcing the PYNQ & RFSoC workshop materials

Matrix Operation Library for FPGA https://xilinx.github.io/gemx/

The Kria Robotics Stack (KRS) is a ROS 2 superset for industry, an integrated set of robot libraries and utilities to accelerate the development, maintenance and commercialization of...

bootgen source code

Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ

AMD Xilinx University Program Vivado tutorial

This store contains Configurable Example Designs.

PYNQ Bootcamp 2019-2026 teaching materials.

AMD Xilinx University Program Embedded tutorial

FPL'26 Optimization Contest

Introductory examples for using PYNQ with Alveo

A research shell for Alveo V80

Networking Overlay on PYNQ

For publishing the source for UG1352 "Get Moving with Alveo"

Repo Manifests for the Yocto Project Build System